GATE Digital Circuits: Combinatorial Circuits – Previous Year Questions
29 GATE previous year questions on Combinatorial Circuits (Digital Circuits, Electronics and Communication Engineering) with answers and explanations, from every paper.
- GATE 2017 EC Q53 – Which one of the following gives the simplified sum of products expression for the Boolean function F = m 0 + m 2 + m 3 + m 5, where m 0, m 2, m 3 and…
- GATE 2015 EC Q46 – The Boolean expression F(X, Y, Z) = XYZ + XYZ + XYZ + XYZ converted into the canonical product of sum (POS) form is
- GATE 2015 EC Q47 – All the logic gates shown in the figure have a propagation delay of 20 ns. Let A = C = 0 and B = 1 until time t = 0. At t = 0, all the inputs flip…
- GATE 2015 EC Q48 – A 3-input majority gate is defined by the logic function M(a, b, c) = ab + bc + ca. Which one of the following gates is represented by the function…
- GATE 2016 EC Q27 – The output of the combinational circuit given below is
- GATE 2016 EC Q52 – Identify the circuit below.
- GATE 2016 EC Q53 – The functionality implemented by the circuit below is
- GATE 2018 EC Q18 – The logic function f(X,Y) realized by the given circuit is
- GATE 2018 EC Q19 – A function F(A,B,C) defined by three Boolean variables A, B and C when expressed as sum of products is given by F= A B C+ A B C+A B C where, A, B, and…
- GATE 2018 EC Q41 – A four-variable Boolean function is realized using 41 multiplexers as shown in the figure. The minimized expression for F(U,V,W,X) is
- GATE 2018 EC Q57 – The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are…
- GATE 2019 EC Q23 – A standard CMOS inverter is designed with equal rise and fall times ( n= p). If the width of the pMOS transistor in the inverter is increased, what…
- GATE 2019 EC Q24 – In the circuit shown, what are the values of F for EN = 0 and EN = 1, respectively?
- GATE 2019 EC Q25 – In the circuit shown, A and B are the inputs and F is the output. What is the functionality of the circuit?
- GATE 2019 EC Q63 – A CMOS inverter, designed to have a mid-point voltage V I equal to half of V dd, as shown in the figure, has the following parameters: V dd=3 V nC…
- GATE 2020 EC Q20 – The figure below shows a multiplexer where S 1 and S 0 are the select lines, I 0 to I 3 are the input data lines, EN is the enable line, and F(P,Q,R)…
- GATE 2021 EC Q41 – The propagation delays of the XOR gate, AND gate and multiplexer (MUX) in the circuit shown in the figure are 4 ns, 2 ns and 1 ns, respectively. If…
- GATE 2022 EC Q19 – Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for A 0, A 1, A 2, and A 3 are .
- GATE 2022 EC Q27 – Select the Boolean function(s) equivalent to x+yz, where x, y, and z are Boolean variables, and + denotes logical OR operation.
- GATE 2022 EC Q28 – Select the correct statement(s) regarding CMOS implementation of NOT gates.
- GATE 2022 EC Q49 – Consider a Boolean gate (D) where the output Y is related to the inputs A and B as, Y=A+ B, where + denotes logical OR operation. The Boolean inputs…
- GATE 2023 EC Q23 – In the circuit shown below, P and Q are the inputs. The logical function realized by the circuit shown below is
- GATE 2024 EC Q19 – For the Boolean function F(A,B,C,D)= m(0,2,5,7,8,10,12,13,14,15), the essential prime implicants are .
- GATE 2024 EC Q40 – A 4-bit priority encoder has inputs D 3, D 2, D 1, and D 0 in descending order of priority. The two-bit output AB is generated as 00, 01, 10, and 11…
- GATE 2025 EC Q23 – A 3-input majority logic gate has inputs X, Y, and Z. The output F of the gate is logic ‘1’ if two or more of the inputs are logic ‘1’. The output F…
- GATE 2025 EC Q24 – A full adder and an XOR gate are used to design a digital circuit with inputs X, Y, and Z, and output F, as shown below. The input Z is connected to…
- GATE 2026 EC Q20 – In the circuit shown in the Figure, A and B are logic inputs and Y is the logic output. Which of the following logic operations is realized by the…
- GATE 2026 EC Q48 – A Boolean function, f(x,y,z) with x as MSB and z as LSB is realized by 4:1 multiplexer (MUX) with select lines, S 1 and S 0 (S 1 is MSB, S 0 is LSB)…
- GATE 2026 EC Q56 – Consider the four-variable Boolean function, f(w,x,y,z)= m(0,2,5,7,8,10,13,14,15) with ‘w’ as MSB and ‘z’ as LSB. Which of the following expressions…