GATE 2017 EC (EC2) – Question 54
Figure I is a 4-bit ripple-carry adder built from full adders; Figure II shows one full-adder circuit. XOR, AND and OR propagation delays are 20 ns, 15 ns and 10 ns, respectively. Initially all inputs are zero.
At t=0, inputs change to $X_3X_2X_1X_0=1100$, $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The adder output is stable at t=________ ns.
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Correct answer: 50.0 to 50.0
Explanation
Use the actual input transition rather than the worst-case four-stage ripple bound. At bits 0 and 1 both operand bits remain zero; neither stage propagates the input carry. Bit 0's sum changes after its final XOR, at 20 ns, while its carry stays zero.
At bit 2, both operand bits become one. Its generate term changes after the 15 ns AND and 10 ns OR, making carry Z3 high at 25 ns. The bit-2 propagate XOR remains zero for the simultaneous equal-input change.
At bit 3, the propagate term becomes one at 20 ns. Combining it with Z3 takes another AND delay followed by the OR delay: $25+15+10=50$ ns for Z4. The bit-3 sum settles by 45 ns.
The last output settles at **50 ns**.