Use four NAND gates: $n_1=\overline{AB}$, $n_2=\overline{An_1}$, $n_3=\overline{Bn_1}$ and $Y=\overline{n_2n_3}$. The output is $A\oplus B$.
The first gate creates the shared product complement; two branches distinguish the unequal-input cases and the final gate combines them. This standard realization needs **four gates, A**; three 2-input NAND gates cannot implement the XOR truth table.
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