GATE 2021 EC – Question 41
The propagation delays of the XOR gate, AND gate and multiplexer (MUX) in the circuit shown in the figure are 4 ns, 2 ns and 1 ns, respectively.
If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is
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Correct answer: (C) 6 ns
Explanation
T drives the select lines of both multiplexers. If $T=0$, the output is the top AND gate through the second MUX, a delay of $2+1=3$ ns. If $T=1$, the first MUX passes the lower AND gate (R, S), so the path is AND ($2$) + MUX ($1$) + AND ($2$) + MUX ($1$) $=6$ ns. The slower path through the XOR gate ($4+1+2+1=8$ ns) is never selected to the output, because when the first MUX selects the XOR the second MUX ignores that branch. So the maximum delay is 6 ns.