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GATE 2016 EE – Question 46

Analog and Digital Electronics · VCOs and timers, combinatorial and sequential logic circuits, multiplexers, demultiplexers · 2 marks · Multiple choice

The current state $Q_A Q_B$ of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is

Two JK flip-flops share a common clock. Flip-flop A has J and K both tied to 5 V. The $\bar{Q}_A$ output of flip-flop A is connected to both the J and K inputs of flip-flop B. The outputs are $Q_A$ and $Q_B$.
  1. 00
  2. 01
  3. 11
  4. 10

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Show answer and explanation

Correct answer: (C) 11

Explanation

Because the clock rise-time is much shorter than the flip-flop delay, both flip-flops see the old outputs at the clock edge. Flip-flop A has $J = K = 1$, so it toggles from 0 to 1. Flip-flop B has $J = K = \bar{Q}_A = 1$ (as $Q_A = 0$ before the edge), so it also toggles from 0 to 1. The next state is $Q_A Q_B = 11$.