The GATE Grind

GATE 2014 EC (EC3) – Question 25

Digital Circuits · Sequential Circuits · 1 mark · Multiple choice

Identify the circuit shown.

Diagram for GATE 2014 EC (EC3) question 25
  1. Toggle flip-flop
  2. JK flip-flop
  3. SR latch
  4. Master–slave D flip-flop

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Show answer and explanation

Correct answer: (D) Master–slave D flip-flop

Explanation

The first D latch is transparent while clock is high, and the second is enabled by the inverted clock. Thus the second holds while the first tracks, then transfers the stored value when the clock falls. Together they form a **master-slave D flip-flop,D**, with falling-edge output behaviour.