GATE 2016 EC (EC3) – Question 55
In the circuit shown, the bubbled NAND gate delay is 2 ns and the counter delay is zero. At a clock frequency of 1 GHz, the counter behaves as a
Practise this question in The GATE Grind →
Show answer and explanation
Correct answer: (D) mod-8 counter
Explanation
The NAND decode becomes active for Q2Q1Q0=100, nominally requesting an asynchronous reset at count 4. At 1 GHz each count lasts only 1 ns.
The decode condition therefore lasts 1 ns, shorter than the gate's 2 ns propagation delay. Under the inertial gate-delay interpretation used by the official answer, that narrow reset pulse is suppressed and no reset reaches the counter.
It continues through all eight 3-bit states, behaving as **mod-8, D**. A pure transport-delay model would behave differently; the key uses pulse rejection by the finite-delay gate.