GATE Digital Circuits: Sequential Circuits – Previous Year Questions
22 GATE previous year questions on Sequential Circuits (Digital Circuits, Electronics and Communication Engineering) with answers and explanations, from every paper.
- GATE 2017 EC Q25 – In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = '0'. If the input…
- GATE 2017 EC Q27 – Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the…
- GATE 2017 EC Q54 – A 4-bit shift register circuit configured for right-shift operation, i.e. D in A, A B, B C, C D, is shown. If the present state of the shift register…
- GATE 2017 EC Q56 – A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of…
- GATE 2018 EC Q29 – A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on…
- GATE 2018 EC Q56 – In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data D in using clock CK. The XOR gate outputs 3.3 volts…
- GATE 2019 EC Q35 – In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12 kHz. The frequency of the signal at Q 2 is kHz.
- GATE 2019 EC Q49 – The state transition diagram for the circuit shown is
- GATE 2020 EC Q49 – The state diagram of a sequence detector is shown below. State S 0 is the initial state of the sequence detector. If the output is 1, then
- GATE 2020 EC Q60 – For the components in the sequential circuit shown below, t pd is the propagation delay, t setup is the setup time, and t hold is the hold time. The…
- GATE 2021 EC Q56 – The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns. The propagation delay of all the flip-flops is assumed to…
- GATE 2022 EC Q43 – For the circuit shown, the clock frequency is f 0 and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, .
- GATE 2023 EC Q24 – The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively,…
- GATE 2023 EC Q34 – For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is (rounded off to the nearest integer).
- GATE 2023 EC Q63 – In a given sequential circuit, initial states are Q 1=1 and Q 2=0. For a clock frequency of 1 MHz, the frequency of signal Q 2 in kHz, is (rounded off…
- GATE 2024 EC Q41 – The propagation delay of the 21 MUX shown in the circuit is 10 ns. Consider the propagation delay of the inverter as 0 ns. If S is set to 1 then the…
- GATE 2024 EC Q42 – The sequence of states (Q 1Q 0) of the given synchronous sequential circuit is .
- GATE 2025 EC Q45 – A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input P0 is set to logic ‘0’ and P1 is set…
- GATE 2025 EC Q62 – In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0…
- GATE 2026 EC Q27 – A binary ripple counter is designed to count (0) 10 to (64) 10. Which of the following is/are the number of flip-flops required to design the counter?
- GATE 2026 EC Q35 – The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of 10 cycles/second is applied to its…
- GATE 2026 EC Q49 – A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops…