GATE 2014 EC (EC2) – Question 50
For the circuit shown, select the output y timing diagram from W1,W2,W3,W4.
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Correct answer: (C) W3
Explanation
The bubbles at both clock inputs mean falling-edge triggering. At successive falling edges the sampled input pairs are(0,0),(1,0),(1,0),(1,1). Their AND outputs are0,0,0,1, held between edges. Only **W3,C** remains low until the last falling edge and then rises. Narrow input changes between active edges do not propagate.