GATE 2016 EC (EC2) – Question 27
All gates in the shown circuit are ideal. $R=10\ \mathrm{k}\Omega$ and the supply is 5 V. D1–D5 start with logic values 0,1,0,1,0, respectively. The clock has a 30% duty cycle. The average power dissipated in R, in mW, is ________.
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Correct answer: 1.45 to 1.55
Explanation
The five flip-flops circulate the initial pattern, giving five equally long states. The resistor is driven by the OR of Q3 and Q5.
Over the five rotations these two taps are simultaneously zero twice and at least one is high three times. Thus the output is high for 3/5 of the total time. Edge-triggered storage means the clock duty cycle does not alter these state durations.
When high, $P=5^2/10000=2.5$ mW; otherwise it is zero. Average power is $(3/5)2.5=$ **1.5 mW**.