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GATE 2026 EC – Question 49

Digital Circuits · Sequential Circuits · 2 marks · Multiple choice

A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay. Which of the following options gives the correct binary representation ($b_7b_6b_5b_4b_3b_2b_1b_0$) of the content of the shift register immediately after the 5th clock transition (positive edge)?

Diagram for GATE 2026 EC question 49
  1. 00011111
  2. 10111111
  3. 00111111
  4. 11000011

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Show answer and explanation

Correct answer: (A) 00011111

Explanation

The serial input to $b_0$ is $Q\oplus1=\bar Q$, and the flip-flop samples $b_7$, which stays 0 for the first 7 shifts. So $Q=0$ and a 1 is shifted in on each of the first 5 clocks, giving 00011111.