GATE 2023 EC – Question 24
The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are
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Correct answer: (A) 1000, 3
Explanation
The three D flip-flops form a pipeline (shift register), so a new bit enters on every clock. The throughput equals the clock frequency, 1 bit per ns $=1000$ Mbit/s. A bit needs 3 clock cycles to pass through the 3 stages, i.e. a latency of $3\times1$ ns $=3$ ns.