GATE 2020 EC – Question 60
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{setup}$ is the setup time, and $t_{hold}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is ________ MHz.
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Correct answer: 77
Explanation
The clock period must cover the longest register-to-register path. The path from Flip-Flop 2 to Flip-Flop 1 is $t_{pd2}+t_{setup1}=8+5=13$ ns. The path from Flip-Flop 1 through the XOR and NAND gates to Flip-Flop 2 is $3+2+2+4=11$ ns. The critical path is 13 ns, so $f_{max}=\frac{1}{13\text{ ns}}=76.9\approx77$ MHz.