GATE 2018 EC – Question 56
In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $\Delta T/T_{CK}=0.15$, where the parameters $\Delta T$ and $T_{CK}$ are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.
If the probability of input data bit ($D_{in}$) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is ________.
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Correct answer: 0.83 to 0.85
Explanation
The output $X$ is the XOR of $D_{in}$ and the flip-flop output $Q$. When $D_{in}$ changes (probability 0.3), it does so $\Delta T$ after the clock edge, so $Q$ still holds the old value for the remaining $T_{CK}-\Delta T=0.85T_{CK}$ of the period, and $X$ is high for that time. The average is $0.3\times0.85\times3.3=0.84$ V.