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GATE 2017 EC – Question 56

Digital Circuits · Sequential Circuits · 2 marks · Multiple choice

A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_A Q_B = 00, 01, 10,$ and 11.

[Figure: The D input of flip-flop A is the exclusive-OR of $Q_A$ and $Q_B$. The D input of flip-flop B is the output of a NAND gate with inputs $Q_A$ and $X_{IN}$. Both flip-flops share the clock CLK.]

Assume that $X_{IN}$ is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state $Q_A Q_B = 00$ and clocked, after a few clock cycles, it starts cycling through

Diagram for GATE 2017 EC question 56
  1. all of the four possible states if $X_{IN} = 1$
  2. three of the four possible states if $X_{IN} = 0$
  3. only two of the four possible states if $X_{IN} = 1$
  4. only two of the four possible states if $X_{IN} = 0$

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Correct answer: (D) only two of the four possible states if $X_{IN} = 0$

Explanation

The next state is $D_A = Q_A \oplus Q_B$ and $D_B = \overline{Q_A \cdot X_{IN}}$. With $X_{IN} = 1$, $D_B = \overline{Q_A}$, and the sequence from 00 is 00, 01, 11, 00, which cycles through three states. With $X_{IN} = 0$, $D_B = 1$ always, so from 00 the machine goes to 01, then 11, then 01, and so on. It then cycles between only two states, 01 and 11.