GATE 2017 EC – Question 27
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output of the latch in percentage is ________.
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Correct answer: 30
Explanation
Take one period $T$. CLK1 is high from 0 to $0.5T$, and CLK2 is high from $0.2T$ to $0.7T$. The latch follows D only while CLK2 is high. During that time D is high from $0.2T$ to $0.5T$ and low from $0.5T$ to $0.7T$, so the output goes high at $0.2T$ and falls at $0.5T$. After $0.7T$ the latch holds the value 0 until $1.2T$. So the output is high for $0.3T$ of each period, a duty cycle of 30%.