GATE 2021 EC – Question 56
The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns. The propagation delay of all the flip-flops is assumed to be zero. The clock (Clk) frequency provided to the circuit is 500 MHz.
Starting from the initial value of the flip-flop outputs $Q_2Q_1Q_0=1\,1\,1$ with $D_2=1$, the minimum number of triggering clock edges after which the flip-flop outputs $Q_2Q_1Q_0$ becomes $1\,0\,0$ (in integer) is ________.
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Correct answer: 5
Explanation
$D_2=Q_2\oplus Q_0$ and the flip-flops shift right ($Q_1^+=Q_2$, $Q_0^+=Q_1$). The clock period is 2 ns, shorter than the 3 ns XOR delay, so the XOR output lags the state: $D_2=1$ (the initial value) for the first two edges, and from the third edge on it is the XOR of the state from three edges earlier. The sequence of states after each edge is: edge 1 ($D_2=1$): 111; edge 2 ($D_2=1$): 111; edge 3 ($D_2=0$): 011; edge 4 ($D_2=0$): 001; edge 5 ($D_2=1$): 100. So 5 clock edges are needed.