The GATE Grind

GATE 2022 EC – Question 43

Digital Circuits · Sequential Circuits · 2 marks · Multiple choice

For the circuit shown, the clock frequency is $f_0$ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ________.

Diagram for GATE 2022 EC question 43
  1. frequency is $f_0/4$ and duty cycle is 50%
  2. frequency is $f_0/4$ and duty cycle is 25%
  3. frequency is $f_0/2$ and duty cycle is 50%
  4. frequency is $f_0$ and duty cycle is 25%

Practise this question in The GATE Grind →

Show answer and explanation

Correct answer: (A) frequency is $f_0/4$ and duty cycle is 50%

Explanation

The J and K inputs are both connected to the counter's LSB, so the flip-flop toggles when LSB $=1$ and holds when LSB $=0$. The LSB alternates $0,1,0,1,\dots$, so Q toggles on every second clock edge. Q therefore has a period of four clock cycles (frequency $f_0/4$) and is high for two of them (50% duty cycle).