GATE 2023 EC – Question 34
For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is ________ (rounded off to the nearest integer).
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Correct answer: 2
Explanation
The circuit is a cross-coupled NAND SR latch. A change at an input must pass through the first NAND to change $Q$, and then through the second NAND (through the feedback) to update $\bar Q$. The longest path has two gates, so the critical path delay is $2\times1$ ns $=2$ ns.