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GATE 2025 EC – Question 62

Digital Circuits · Sequential Circuits · 2 marks · Numerical answer

In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns.

The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is ________.

Diagram for GATE 2025 EC question 62

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Correct answer: 200

Explanation

The critical path is flip-flop 2 output $\to$ AND gate $\to$ flip-flop 1 input: $T_{clk}\ge t_{cq}+t_{AND}+t_{su}=2+1+2=5$ ns. The other path (flip-flop 1 to flip-flop 2) needs only $2+2=4$ ns. So $f_{max}=1/5\text{ ns}=200$ MHz.