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GATE 2023 EE – Question 56

Analog and Digital Electronics · VCOs and timers, combinatorial and sequential logic circuits, multiplexers, demultiplexers · 2 marks · Numerical answer

Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with clock, is ____________.

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Correct answer: 8

Explanation

Let the flip-flop outputs be $Q_1$ (left, with $\bar Q_1=A$) and $Q_2$ (right, with $Q_2=C$). The NOR with both inputs tied to $A$ gives $B=\bar A=Q_1$. The XOR gives $D=B\oplus C=Q_1\oplus Q_2$. The flip-flop inputs are $D_1=C=Q_2$ and $D_2=D$. So at each clock $(Q_1,Q_2)\to(Q_2,\ Q_1\oplus Q_2)$. The state is unchanged only if $Q_2=Q_1$ and $Q_1\oplus Q_2=Q_2$; the second condition gives $Q_1=0$, so $Q_1=Q_2=0$. Then $A=1$, $B=0$, $C=0$, $D=0$, i.e. $ABCD=1000_2=8$.