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GATE 2021 EE – Question 32

Analog and Digital Electronics · VCOs and timers, combinatorial and sequential logic circuits, multiplexers, demultiplexers · 1 mark · Numerical answer

A 16-bit synchronous binary up-counter is clocked with a frequency $f_{CLK}$. The two most significant bits are OR-ed together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is 24 ms. The clock frequency $f_{CLK}$ is ________ MHz. (Round off to 2 decimal places.)

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Correct answer: 2.04 to 2.06

Explanation

Y is low only while both MSBs are 0, i.e. for the first quarter of the $2^{16}$ counts, and high for the remaining three quarters. So Y is high for $\frac34\times2^{16}=49152$ clock periods, which equal 24 ms. Hence $f_{CLK}=\frac{49152}{0.024}=2.048$ MHz.