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GATE 2018 EE – Question 24

Analog and Digital Electronics · VCOs and timers, combinatorial and sequential logic circuits, multiplexers, demultiplexers · 1 mark · Multiple choice

In the logic circuit shown in the figure, Y is given by

Diagram for GATE 2018 EE question 24
  1. $Y=ABCD$
  2. $Y=(A+B)(C+D)$
  3. $Y=A+B+C+D$
  4. $Y=AB+CD$

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Correct answer: (D) $Y=AB+CD$

Explanation

The first-level NAND gates give $\overline{AB}$ and $\overline{CD}$, and the output NAND gives $Y=\overline{\overline{AB}\cdot\overline{CD}}=AB+CD$.