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GATE 2022 EE – Question 29

Analog and Digital Electronics · VCOs and timers, combinatorial and sequential logic circuits, multiplexers, demultiplexers · 1 mark · Numerical answer

The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propagation delay of 20 ns, is ________. (round off to one decimal place)

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Correct answer: 12.44 to 12.56

Explanation

In a ripple counter the delays of the stages add up, so the clock period must be at least $4\times20=80$ ns. So $f_{max}=\frac{1}{80\text{ ns}}=12.5$ MHz.