GATE 2026 BM – Question 64
In the shown cross-coupled NAND circuit, each NAND delay is 4 ns and the NOT delay is 1 ns. Input is a 10 MHz clock with 50% duty cycle. Find the output duty cycle as an integer percentage.
Practise this question in The GATE Grind →
Show answer and explanation
Correct answer: 55 to 55
Explanation
The period is 100 ns with fifty-nanosecond input half-cycles. A falling input makes the upper NAND output rise after four ns. A rising input must propagate through the inverter and lower NAND before the upper NAND falls, taking 1+4+4=9 ns. Thus the output remains high for 50+9−4=55 ns per period, giving 55%.