GATE 2023 EC – Question 64
In the circuit below, the voltage $V_L$ is ________ V (rounded off to two decimal places).
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Show answer and explanation
Correct answer: 1.99 to 2.01
Explanation
The 1 mA reference flows in the diode-connected PMOS with $W/L=1$. The PMOS with $W/L=10$ mirrors 10 mA, and the PMOS with $W/L=7$ mirrors 7 mA. The 10 mA feeds the diode-connected NMOS ($W/L=10$), and the NMOS with $W/L=5$ mirrors half of that: 5 mA. At node $V_L$, 7 mA is supplied from the top and 5 mA is pulled down by the NMOS, so the net 2 mA flows through the 1 kΩ resistor: $V_L=2\text{ mA}\times1\text{ k}\Omega=2.00$ V (all transistors assumed in saturation).