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GATE 2026 EE – Question 46

Analog and Digital Electronics · VCOs and timers, combinatorial and sequential logic circuits, multiplexers, demultiplexers · 2 marks · Multiple choice

The MOSFET switches shown in the circuit are ideal.

Which of the following is the correct option for Boolean logical expression of the output (OUT), and the maximum possible power (P) consumed by the circuit?

Diagram for GATE 2026 EE question 46
  1. $\text{OUT}=\overline{AB+\bar C}$, $P=5$ mW
  2. $\text{OUT}=\overline{(A+B)\bar C}$, $P=5$ mW
  3. $\text{OUT}=\overline{AB\bar C}+\bar C$, $P=7.5$ mW
  4. $\text{OUT}=\overline{AB}\,C$, $P=7.5$ mW

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Show answer and explanation

Correct answer: (D) $\text{OUT}=\overline{AB}\,C$, $P=7.5$ mW

Explanation

OUT is pulled down by the series transistors $A,B$ (when $AB=1$) and by the middle transistor whose gate is the node of the 10 kΩ resistor, which is high exactly when $C=0$. So OUT is low if $AB=1$ or $\bar C=1$: $\text{OUT}=\overline{AB+\bar C}=\overline{AB}\cdot C$. The maximum power occurs when OUT is low with $AB=1$ (the 5 kΩ carries 1 mA: 5 mW) and $C=1$ (the 10 kΩ carries 0.5 mA: 2.5 mW). The total is $5+2.5=7.5$ mW, which is option D.