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GATE 2020 EC – Question 46

Analog Circuits · BJT and MOSFET Amplifiers · 2 marks · Multiple choice

An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to $-10$ V. If the input voltage $V_I$ lies between $\pm10$ V, the minimum and the maximum values of $V_G$ required for proper sampling and holding respectively, are

Diagram for GATE 2020 EC question 46
  1. 3 V and $-3$ V.
  2. 10 V and $-10$ V.
  3. 13 V and $-7$ V.
  4. 10 V and $-13$ V.

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Show answer and explanation

Correct answer: (C) 13 V and $-7$ V.

Explanation

The NMOS switch must turn on for every input in $\pm10$ V when $V_G$ is high, and must be off for every input when $V_G$ is low. To be on at $V_I=+10$ V the gate must be at least $10+3=13$ V. To be off at $V_I=-10$ V (the most negative input, so the largest $V_{GS}$ for a given $V_G$) the gate must be at most $-10+3=-7$ V. So the gate swings between $13$ V and $-7$ V.